Due to the recent tendency for semiconductor elements to become small, it becomes indispensable to develop minute multi-layered wirings for fabricating a semiconductor device. Consequently. it is now very important to flatten the surface of an intermetal dielectric layer of a semiconductor device having multi-layered wirings.
Moreover, if there is difference in level on the surface of the intermetal dielectric layer, a minute resist pattern for forming a wiring layer thereon cannot be made up because of insufficiency of focus-margin in photolithography. Even when the resist pattern can be made up by chance, there arise the breaking of the wire in the wiring layer and a non-etched portion of the wiring materiel at the point of difference in level. Accordingly, it is necessary to flatten the surface of the intermetal dielectric layer
Accordingly, the SOG layer is used as the intermetal dielectric layer to improve various aspects of the semiconducter. However, inorganic SOG, which is composed of four member ring siloxsane functional groups, and organic SOG, which is composed of three member ring siloxsane functional groups comprising methyl or ethyl radicals, have been used as such SOG layers. However, inorganic SOG is apt to be cracked in thermal treatment and organic SOG is apt to be cracked-resisting properties, but methyl or ethyl radicals are deteriorated, when exposed to oxygen plasma.
In recent years, SOG comprising silazane bondings in its backbone (polysilazane SOG, hereinafter) was developed as SOG having crack-resisting and oxygen plasma-resisting properties, and disclosed in Japanes Patent Kokai 5-243223. This SOG is sintered in an oxidizing atmosphere, such as water vapor, releases amino-compound gas, such as ammonia, and is converted into an oxidized layer with high quality.
However, when the processed substrate in sintered, the wiring layer composed of aluminum, etc. is corroded by water vapor (sintering atmosphere gas) or amino-compound gas, and reliability of the wiring layer is noticeably degraded. Under excess oxidization treatment, oxidizing gas penetrates the intermetal dielectric layer, which is ordinarily porous, and even the surface of a silicon substrate is oxidized.
Thereupon, in order to prevent corrosion of the aluminum wiring layer, water absorption treatment or ultraviolet irradiation is applied to the surface of the polysilazane SOG layer in the process of sintering. This method is disclosed in Japanese Patent Kokai No. 7-45605 in detail. Moreover, a method for depositing a silicon nitride layer (a SiN layer, hereinafter) or a silicon oxinitride layer (a SiON layer, hereinafter) with high passivation effect on the wiring layer is disclosed in Japanese Patent Kokai 8-115910. In this structure, the passivation layer isolates water vapor (sintering atmosphere gas) and amino-compound gas (out gas) from the wiring layer.
In a semiconductor device disclosed in Japanese Patent Kokai 8-11590, an underlying insulator layer is formed on a silicon substrate, and the first wiring layer is formed on the underlying insulator layer. The first wiring layer is composed of aluminum. Next, a SiON layer is so formed that the whole surfaces of the first wiring layer and the underlying insulator layer are covered with the SiON layer. The SiON layer is deposited by a chemical vapor deposition method in a plasmic atmosphere. Next, polysilazane SOG application is applied to the whole surfaces of the first wiring layer on the underlying insulator layer. Then, the processed substrate is sintered and a polysilazane SOG layer is formed. Next, a through hole is formed on a predetermined region on the polysilazane SOG layer and the SiON layer, through which the second wiring layer formed on the top surface of the polysilazane SOG layer is electrically connected with the first wiring layer.
However, according to the method disclosed in Japanese Patent Kokai No. 7-45605, it is difficult to sufficiently oxidize the polysilazane SOG layer. Then, it becomes difficult to obtain a dense oxidized layer with high quality serving as an intermetal dielectric layer. Especially, when the polysilazane SOG layer is thick, quality of its interior part is degraded.
If the period of sintering is elongated in order to sufficiently oxidize the polysilazane SOG layer, the surface of the wiring layer is corroded by oxidizing gas, and reliability of the wiring layer is noticeably degraded.
According to the technology disclosed in Japanese Patent Kokai 8-115910, the SiON layer serving as the passivation layer is formed between the first wiring layer and the second wiring layer. It should be noted that the dielectric constant of the passivation layer is considerably higher than that of a silicon oxide layer. Accordingly, parasitic capacitance between the wiring layers increases, which checks the improvement of speed of data-processing of the semiconductor device. This problem becomes noticeable as the structure of the wiring layer becomes minute.
Moreover, in an ordinary method for fabricating a semiconductor device, thermal treatment is applied to a processed substrate in a hydrogen atmosphere after wiring layers are formed. This process is indispensable in order to stabilize the characteristics of a MOS transistor. By the above mentioned thermal treatment, non-bonded sites on a boundary surface between the insulator layer of the MOS transistor and the silicon substrate are terminated by hydrogen.
Moreover, if the passivation layer is formed on the whole surfaces of the wiring layer and the underlying layer as in the case of the technology shown in Japanese Patent Kokai 8-115910, thermal treatment of the processed substrate in hydrogen atmosphere is not effectual, and the characteristics of the MOS transistor cannot be stabilized. The reason is that the passivation layer obstructs penetration of hydrogen into the interior region of the processed substrate.